# How to Design a 4-Bit BCD Adder in Verilog at Behavioral level Modeling

**BCD Adder:**

Consider the arithmetic addition of two decimal digits in BCD, together with an input carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than 9+9+1=19, the 1 in the sum being an input carry. Suppose we apply two BCD digits to a four-bit binary adder. The adder will form the sum in binary and produce a result that ranges from 0 through 19. These binary numbers are listed in Table given below and are labeled by symbols K, Z8, Z4, Z2, and Z1. K is the carry, and the subscripts under the letter Z represent the weights 8, 4, 2, and 1 that can be assigned to the four bits in the BCD code. The columns under the binary sum list the binary value that appears in the outputs of the four-bit binary adder. The output sum of two decimal digits must be represented in BCD and should appear in the form listed in the columns under “BCD Sum.” The problem is to find a rule by which the binary sum is converted to the correct BCD digit representation of the number in the BCD sum.

In examining the contents of the table, it becomes apparent that when the binary sum is equal to or less than 1001, the corresponding BCD number is identical, and therefore no conversion is needed. When the binary sum is greater than 1001, we obtain an invalid BCD representation. The addition of binary 6 (0110) to the binary sum converts it to the correct BCD representation and also produces an output carry as required.

The logic circuit that detects the necessary correction can be derived from the entries in the table. It is obvious that a correction is needed when the binary sum has an output carry K=1. The other six combinations from 1010 through 1111 that need a correction have a 1 in position Z8. To distinguish them from binary 1000 and 1001, which also have a 1 in position Z8, we specify further that either Z4 or Z2 must have a 1. The condition for a correction and an output carry can be expressed by the Boolean function.

C=K+Z8Z4+Z8Z2

When C=1, it is necessary to add 0110 to the binary sum and provide an output carry for the next stage.

A BCD adder that adds two BCD digits and produces a sum digit in BCD is shown in Figure below. The two decimal digits, together with the input carry, are first added in the top four-bit adder to produce the binary sum. When the output carry is equal to 0, nothing is added to the binary sum. When it is equal to 1, binary 0110 is added to the binary sum through the bottom four-bit adder. The output carry generated from the bottom adder can be ignored, since it supplies information already available at the output carry terminal. A decimal parallel adder that adds n decimal digits needs n BCD adder stages.

The output carry from one stage must be connected to the input carry of the next higher order stage.

The Logic Diagram is given by:

**Verilog Code:**

`module bcdadder(out,in1,in2,cin);`

input [3:0]in1,in2;

input cin;

output [3:0]out;

reg [3:0]out;

integer cout,carry;

always @ (in1 or in2)

begin

{cout,out}=in1+in2+cin;

carry=(cout|(out[3] & out[2])|(out[3] & out[1]));

if(carry==1'b1)

out=out+4'b0110;

else

out=out+4'b0000;

end

endmodule

If you have further questions feel free to ask by commenting below….Thanks!

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Thanks for the complements, Stay Tuned for more.

how i design a BCD adder using test bench modeling in verilog??? please send me the solution in my e-mail (tajmul.eee.cuet@gmail.com)..

with thanks

Kazi Tajmul Islam

We will come with solution after this weekend.

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that I think I would never understand. It seems too complicated and extremely broad

for me. I am looking forward for your next post, I will try to get the hang of

it!

We always try to make it as simple as we can so that the beginners and students can easily understand. Stay connected and keep visiting for more.

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Thanks for your kind words…. Stay connected for more.

need to change the figure excess-3 with K coloumn figüre.

i couldn’t understand this . {cout,out}=in1+in2+cin;

thank u.

And i want to receive test bench. Could you give me test bench file?

rngksgh@naver.com

Ok, check your inbox soon. cheers